Over 40 publications using NanoIntegris materials.
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Radio Frequency and Linearity Performance of Transistors Using High-Purity Semiconducting Carbon Nanotubes
Summary: This paper reports the radio frequency (RF) and linearity performance of transistors using high-purity semiconducting carbon nanotubes. High-density, uniform semiconducting nanotube networks are deposited at wafer scale using our APTES-assisted nanotube deposition technique, and RF transistors with channel lengths down to 500 nm are fabricated. We report on transistors exhibiting a cutoff frequency (ft) of 5 GHz and with maximum oscillation frequency (fmax) of 1.5 GHz. Besides the cutoff frequency, the other important figure of merit for the RF transistors is the device linearity. For the first time, we report carbon nanotube RF transistor linearity metrics up to 1 GHz. Without the use of active probes to provide the high impedance termination, the measurement bandwidth is therefore not limited, and the linearity measurements can be conducted at the frequencies where the transistors are intended to be operating. We conclude that semiconducting nanotube-based transistors are potentially promising building blocks for highly linear RF electronics and circuit applications.
Air-Stable Conversion of Separated Carbon Nanotube Thin-Film Transistors from p-Type to n-Type Using Atomic Layer Deposition of High-κ Oxide and Its Application in CMOS Logic Circuits
Summary: Due to extraordinary electrical properties, preseparated, high purity semiconducting carbon nanotubes hold great potential for thin-film transistors (TFTs) and integrated circuit applications. One of the main challenges it still faces is the fabrication of air-stable n-type nanotube TFTs with industry-compatible techniques. Here in this paper, we report a novel and highly reliable method of converting the as-made p-type TFTs using preseparated semiconducting nanotubes into air-stable n-type transistors by adding a high-κ oxide passivation layer using atomic layer deposition (ALD). The n-type devices exhibit symmetric electrical performance compared with the p-type devices in terms of on-current, on/off ratio, and device mobility. Various factors affecting the conversion process, including ALD temperature, metal contact material, and channel length, have also been systematically studied by a series of designed experiments. A complementary metal−oxide−semiconductor (CMOS) inverter with rail-to-rail output, symmetric input/output behavior, and large noise margin has been further demonstrated. The excellent performance gives us the feasibility of cascading multiple stages of logic blocks and larger scale integration. Our approach can serve as the critical foundation for future nanotube-based thin-film macroelectronics.
High-performance Local Back Gate Thin-Film Field-Effect Transistors Using Sorted Carbon Nanotubes on an Amino-Silane Treated Hafnium Oxide Surface
Summary: Wafer-scale fabrication and characterization of local back gate semiconducting nanotube thin-film transistors (SN-TFTs) are reported in this paper. The local back gate voltage of the corresponding SN-TFT controls the individual transistor switching. In order to achieve high performance, a high-k dielectric material is employed as a gate oxide and this helped to achieve low-voltage operations, much steeper sub-threshold voltage swings and higher transconductance values. A simple procedure to deposit a high-density single-walled carbon nanotube thin film on an amino-silane-treated hafnium oxide (HfOX) surface is suggested such that a good density of nanotubes is realized without degrading the device on–off current ratio and mobility values. The density of the nanotubes achieved on the silanized HfOX surface is about 40–45 nanotubes µm−2. SN-TFTs exhibit an excellent p-type output characteristic with distinct linear and saturation regions. Local back gate SN-TFTs exhibit an on–off current ratio exceeding 104 and a steep sub-threshold slope of 400 mV/decade. SN-TFTs achieve a maximum current density of 13 μA µm−1, an average threshold voltage of −0.5 V, a maximum normalized transconductance of 18.5 μS µm−1 and exhibit a maximum carrier mobility of 60.6 cm2(Vs)−1.
Fabricating Devices with Dielectrophoretically Assembled, Suspended Single Walled Carbon Nanotubes for Improved Nanoelectronic Device Characterization
Integrating carbon nanotubes (CNTs) and nanowires into devices for sensing, actuation and other nanoelectronic applications has the potential to increase device efficiency and lower power consumption. Examples include ultra-high frequency CNT filters and resonators for high sensitivity gas/mass detection. Reliable operation requires careful mechanical and electrical characterization of the integrated CNTs and their contact with electrodes. In this work, we demonstrate a fabrication strategy and integration of suspended single walled CNTs (SWCNTs) on a chip for investigation of the metal nanotube interfacial adhesion strength. A multi-step etching process is used to prepare SWCNTs integrated on TEM compatible chips. Alternating current (AC) dielectrophoresis (DEP) is used for selective SWCNT integration simultaneously overcoming localization issues. The suspended tubes are conducive to mechanical manipulation or electrostatic actuation. In addition, our approach provides fully suspended electrodes for TEM analysis with reduced charging issues that are typically caused by supporting insulating layers. This enables the visualization of failure modes of the tube/electrode contact that have not been previously observed.
Scalable Complementary Logic Gates with Chemically Doped Semiconducting Carbon Nanotube Transistors
Summary: Use of random network carbon nanotube (CNT) transistors and their applications to complementary logic gates have been limited by several factors such as control of CNT density, existence of metallic CNTs producing a poor yield of devices, absence of stable n-dopant and control of precise position of the dopant, and absence of a scalable and cost-effective fabrication process. Here, we report a scalable and cost-effective fabrication of complementary logic gates by precisely positioning an air-stable n-type dopant, viologen, by inkjet printing on a separated semiconducting CNTs network. The obtained CNT transistors showed a high yield of nearly 100% with an on/off ratio of greater than 103 in an optimized channel length (9 μm). The n-doped semiconducting carbon nanotube transistors showed a nearly symmetric behavior in the on/off current and threshold voltage with p-type transistors. CMOS inverter, NAND, and NOR logic gates were integrated on a HfO2/Si substrate using the n/p transistor arrays. The gain of inverter is extraordinarily high, which is around 45, and NAND and NOR logic gates revealed excellent output on and off voltages. These series of whole processes were conducted under ambient conditions, which can be used for large-area and flexible thin film technology.
Fundamental Limits on the Mobility of Nanotube-Based Semiconducting Inks
Summary: High mobility and high on/off ratio thin-film transistors are fabricated using solution-based deposition of purified semiconducting carbon nanotubes. A comprehensive spectrum of the density starting from less than 10 tubes μm-2 to the high end of around 100 tubes μm-2 is investigated. This study provides the first important roadmap for the tradeoffs between mobility and on/off ratio in nanotube-based semiconducting inks.
Effect of Source, Surfactant, and Deposition Process on Electronic Properties of Nanotube Arrays
Summary: The electronic properties of arrays of carbon nanotubes from several different sources differing in the manufacturing process used with a variety of average properties such as length, diameter, and chirality are studied. We used several common surfactants to disperse each of these nanotubes and then deposited them on Si wafers from their aqueous solutions using dielectrophoresis. Transport measurements were performed to compare and determine the effect of different surfactants, deposition processes, and synthesis processes on nanotubes synthesized using CVD, CoMoCAT, laser ablation, and HiPCO.
Radiation Effects in Single-Walled Carbon Nanotube Thin-Film-Transistors
Summary: The fabrication, characterization, and radiation response of single-walled carbon nanotube (SWCNT) thin-film field effect transistors (SWCNT-TFTs) has been performed. SWCNT-TFTs were fabricated on SiO2-Si substrates from 98% pure semiconducting SWCNTs separated by density gradient ultracentrifugation. Optical and Raman characterization, in concert with measured drain current Ion/Ioff ratios, up to 104, confirmed the high enrichment of semiconducting-SWCNTs. Total ionizing dose (TID) effects, up to 10 MRads, were measured in situ for a SWCNT-TFT under static vacuum. The results revealed a lateral translation of the SWCNT-TFT transfer characteristics to negative gate bias resulting from hole trapping within the SiO2 and SiO2-SWCNT interface. Additional TID exposure conducted in air on the same device had the opposite effect, shifting the transfer characteristics to higher gate voltage, and increasing the channel conductance. No significant change was observed in the device mobility or the SWCNT Raman spectra following a TID exposure of 10 Mrad(Si), indicating extrinsic factors dominate the transfer characteristics in the SWCNT-TFT devices during irradiation. The extrinsic effects of charge trapping and the role that gas adsorption plays in the radiation response are discussed.
The Polarized Carbon Nanotube Thin Film LED
Application: Optoelectronic Devices, Transistors
Citation: Megumi Kinoshita, Mathias Steiner, Michael Engel, Joshua P. Small, Alexander A. Green, Mark C. Hersam, Ralph Krupke, Emilio E. Mendez, Phaedon Avouris, Opt. Express (2010), 18, 25, 25738-25745.
Summary: We demonstrate a light emitting p-i-n diode made of a highly aligned film of separated (99%) semiconducting carbon nanotubes, self- assembled from solution. By using a split gate technique, we create p- and n-doped regions in the nanotube film that are separated by a micron-wide gap. We inject p- and n-type charge carriers into the device channel from opposite contacts and investigate the radiative recombination using optical micro-spectroscopy. We find that the threshold-less light generation efficiency in the intrinsic carbon nanotube film segment can be enhanced by increasing the potential drop across the junction, demonstrating the LED- principle in a carbon nanotube film for the first time. The device emits infrared light that is polarized along the long axes of the carbon nanotubes that form the aligned film.
Flexible, Transparent Single-Walled Carbon Nanotube Transistors with Graphene Electrodes
Summary: This paper reports a mechanically flexible, transparent thin film transistor that uses graphene as a conducting electrode and single-walled carbon nanotubes (SWNTs) as a semiconducting channel. These SWNTs and graphene films were printed on flexible plastic substrates using a printing method. The resulting devices exhibited a mobility of ~ 2 cm2 V -1 s -1, On/Off ratio of ~ 102, transmittance of ~ 81% and excellent mechanical bendability.
Macroelectronic Integrated Circuits Using High-Performance Separated Carbon Nanotube Thin-Film Transistors
Summary: Macroelectronic integrated circuits are widely used in applications such as flat panel display and transparent electronics, as well as flexible and stretchable electronics. However, the challenge is to find the channel material that can simultaneously offer low temperature processing, high mobility, transparency, and flexibility. Here in this paper, we report the application of high-performance separated nanotube thin-film transistors for macroelectronic integrated circuits. We have systematically investigated the performance of thin- film transistors using separated nanotubes with 95% and 98% semiconducting nanotubes, and high mobility transistors have been achieved. In addition, we observed that while 95% semiconducting nanotubes are ideal for applications requiring high mobility (up to 67 cm2 V-1 s-1) such as analog and radio frequency applications, 98% semiconducting nanotubes are ideal for applications requiring high on/off ratios (>104 with channel length down to 4µm). Furthermore, integrated logic gates such as inverter, NAND, and NOR have been designed and demonstrated using 98% semiconducting nanotube devices with individual gating, and symmetric input/output behavior is achieved, which is crucial for the cascading of multiple stages of logic blocks and larger scale integration. Our approach can serve as the critical foundation for future nanotube-based thin-film macroelectronics.
Wafer-Scale Fabrication of Separated Carbon Nanotube Thin-Film Transistors for Display Applications
Summary: This paper demonstrates a functioning OLED display device based on a waferscale assembly of carbon nanotube thinfilm transistors. Using IsoNanotubes S 95%, the University of California produced transistors with high yield (>98%), low sheet resistance (25kΩ/sq), high current density ( 10µA/µm), and superior mobility (52 cm 2 V-1s-1). Moreover, on/off rations of >10^4 were achieved in devices with channel length L>20µm. To the best of our knowledge, these are the best concurrent CNT transistor numbers reported in the literature to date.
Thin Film Nanotube Transistors Based on Self-Assembled, Aligned Semiconducting Carbon Nanotube Arrays
Summary: The IBM T.J. Watson Research Center with Northwestern University fabricated thin-film transistors (TFTs) from DGU produced semiconducting CNTs. To confirm the semiconducting purity of the CNTs, the team synthesized 83 single nanotube transistors from the same DGU produced source material. 82 of the 83 transistors were found to contain a semiconducting nanotube, empirically confirming the material's calculated level (99%) of semiconducting enrichment.
80 GHz Field-Effect Transistors Produced Using High Purity Semiconducting Single-Walled Carbon Nanotubes
Summary: In this study, solutions of 99% pure semiconducting nanotubes were used to fabricate SWNT field-effect transistors (FETs) with extrinsic and intrinsic current gain cutoff frequencies of ~15 and ~80 GHz, respectively. Importantly, this study also demonstrates that precise nanotube alignment is not required to achieve excellent performance in high-frequency devices.